The present invention generally relates to Josephson devices and more particularly to a Josephson logic gate having a multiple-input construction. The present invention is related also to a Josephson logic circuit wherein such a Josephson logic gate is used.
The Josephson devices are characterized by extremely fast operational speed and low power consumption. Thus, the device is suitable for super-fast computers or processors, and intensive efforts have been made to construct various digital circuits based upon a Josephson integrated circuit. In the Josephson integrated circuits, the logic gates are generally constructed in the form of AND gate and OR gate elements.
Conventionally, these Josephson logic gates have been constructed to have one or two input ports for the input logic signals. Hereinafter, the problem associated with the Josephson logic gates having multiple input ports will be examined briefly.
FIG. 1 shows an example of the simplest Josephson gate having a single input port A.
Referring to FIG. 1, the Josephson gate includes two Josephson junctions J11 and J12 that are arranged, together with first and second superconducting windings La and Lb, to form a closed loop 1 that acts as a superconducting interferometer. At a node where the windings La and Lb are connected, an a.c. bias current I.sub.g is supplied from a bias terminal 20 via a resistor R, and the bias current thus supplied is caused to flow to a superconducting ground plane GND via a first current path including the winding La and the Josephson junction J.sub.1 and further via a second current path including the winding Lb and the Josephson junction J.sub.2. The input logic signal is supplied to an input line 21 via an input port A, wherein the input line 21 includes inductances La' and Lb' that cause a magnetic coupling respectively with the windings La and Lb of the superconducting loop 1. Thereby, the Josephson junctions J11 and J12 experience a transition to a finite voltage state according to a characteristic curve shown in FIG. 2. In the device of FIG. 1, the output is obtained at the node where the resistor R is connected to the superconducting loop 1.
Referring to FIG. 2 showing the relationship between the input current I.sub.c and the bias current I.sub.g, the Josephson junctions J11 and J12 undergo the transition to the finite voltage state in the region designated in FIG. 2 by hatching. Thus, when the bias current I.sub.g is held constant, the increase in the current I.sub.c causes the switching by crossing the characteristic curve, wherein the threshold value of the current I.sub.c at which the foregoing transition occurs increases with decreasing current I.sub.g. In the Josephson gate of the two-junction construction described above, however, there exists a problem in that the region of the finite voltage state is relatively limited. Associated therewith, the operational (i.e., operating) margin of the device is limited. This problem becomes particularly conspicuous when the number of the input lines is increased.
FIG. 3 shows another typical Josephson logic gate that uses a superconducting interferometer loop 2 wherein three Josephson junctions J11, J12 and J13 are included together with superconducting windings La and Lb. In this case, too, the input logic signal supplied to the line 21 via an input port A is transferred to the loop 2 as a result of the magnetic coupling of inductances La' and Lb' included in the line 21 with the corresponding superconducting windings La and Lb of the loop 2. In the gate of this example, the bias current I.sub.g is supplied from the bias terminal 20 to respective midpoints of the windings La and Lb via the resistor R, and the bias current thus supplied is caused to flow to the superconducting ground plane GND via the Josephson junctions J11, J12 and J13. Thereby, the device shows an operational characteristic as represented in FIG. 4. There, the output of the gate is obtained at the node where the resistor R is connected to the superconducting windings La and Lb.
In the characteristic curve shown in FIG. 4, too, the region of the finite voltage state of the Josephson junctions J11-J13 is indicated by the hatching. In this case, the region of the finite voltage state is expanded as compared with the characteristic curve shown in FIG. 2. Thus, the device of FIG. 3 shows an improved operational margin as compared with the device of FIG. 1.
Using the improved operational margin, the device of FIG. 3 is used successfully to construct the dual input AND gate. There, another input line is provided in magnetic coupling with the interferometer loop 2, and the bias current I.sub.g is set such that the transition occurs only when the input current is supplied to both input lines simultaneously. Further, there is an attempt to construct a Josephson AND gate that has three or more input ports based upon the device of FIG. 3 (Hatano, Y. et al. IEEE J. Solid-State Circuits, Vol.sc-22, No.4, Aug. 1987).
FIG. 5 shows such a three-input Josephson AND gate constructed based upon the superconducting interferometer 2 of FIG. 3, wherein there are provided three input lines 21-23 respectively connected to input ports A-C. There, the bias current I.sub.g is set to a magnitude such that the transition of the Josephson junctions J11-J13 occurs only when the input current is caused to flow simultaneously through the input lines 21-23 in correspondence to the logic state wherein the logic data "1" is supplied simultaneously to the input ports A-C.
In the multiple-input Josephson AND gate that is constructed based on the superconducting interferometer loop 2 of FIG. 3, however, it will be easily understood that there exists a problem of the operational margin becoming increasingly smaller with an increasing number of input lines. More specifically, the tolerance in the variation of the input current becomes increasingly stringent, as it is the sum of the input currents that cause the transition of the Josephson junctions. Thereby, the logic gate becomes increasingly vulnerable to noises and the risk of erroneous operation increases substantially.